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4-51 features ? external power down pin ? central office quality dtmf transmitter/ receiver ? low power consumption ? high speed adaptive micro interface ? adjustable guard time ? automatic tone burst mode ? call progress tone detection to -30dbm ? dtmf transmitter/receiver power down via register control applications ? credit card systems ? paging systems ? repeater systems/mobile radio ? interconnect dialers ? personal computers description the mt8885 is a monolithic dtmf transceiver with call progress filter. it is fabricated in cmos technology offering low power consumption and high reliability. the receiver section is based upon the industry standard mt8870 dtmf receiver while the transmitter utilizes a switched capacitor d/a converter for low distortion, high accuracy dtmf signalling. internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. a call progress filter can be selected allowing a microprocessor to analyze call progress tones. the mt8885 utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. the mt8885 provides enhanced power down features. the transmitter and receiver may independently be powered down via register control. a full chip power down pin provides simple power and control capability. figure 1 - functional block diagram tone in+ in- gs osc1 osc2 v dd v ref v ss est st/gt d0 d1 d2 d3 irq /cp ds/rd cs r/w /wr rs0 ? d/a converters row and column counters transmit data register data bus buffer tone burst gating cct. + - oscillator circuit bias circuit control logic digital algorithm and code converter control logic steering logic status register control register a control register b receive data register interrupt logic i/o control low group filter high group filter dial tone filter pwdn issue 1 may 1995 mt8885 integrated dtmf transceiver with power down & adaptive micro interface ordering information MT8885AE 24 pin plastic dip mt8885an 24 pin ssop mt8885ap 28 pin plcc -40c to +85c advance information
mt8885 advance information 4-52 figure 2 - pin connections pin description pin # name description 24 28 11 in+ non-inverting op-amp input. 22 in- inverting op-amp input. 34 gs gain select . gives access to output of front end differential amplifier for connection of feedback resistor. 46 v ref reference voltage output (v dd /2). 57 v ss ground (0v). 68 osc1 oscillator input. this pin can also be driven directly by an external clock. 79 osc2 oscillator output. a 3.579545 mhz crystal connected between osc1 and osc2 completes the internal oscillator circuit. leave open circuit when osc1 is driven externally. 10 12 tone output from internal dtmf transmitter. 11 13 r / w ( wr ) (motorola) read/write or (intel) write microprocessor input. cmos compatible. 12 14 cs chip select input. this signal must be qualified externally by either address strobe (as), valid memory address (vma) or address latch enable (ale) signal, see figure 12. 13 15 rs0 register select input. refer to table 3 for bit interpretation. cmos compatible. 14 17 ds ( rd ) (motorola) data strobe or (intel) read microprocessor input. activity on this input is only required when the device is being accessed. cmos compatible. 15 18 irq /cp interrupt request/call progress (open drain) output. in interrupt mode, this output goes low when a valid dtmf tone burst has been transmitted or received. in call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. the input signal must be within the bandwidth limits of the call progress filter, see figure 8. 16 19 pwdn power down (input). active high. powers down the device and inhibits the oscillator. irq and tone output are high impedance. data bus is held in tri-state. this pin is internally pulled down. 14- 17 18- 21 d0-d3 microprocessor data bus. high impedance when cs = 1 or ds =0 (motorola) or rd = 1 (intel). ttl compatible. 18 22 est early steering output. presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). any momentary loss of signal condition will cause est to return to a logic low. 19 23 st/gt steering input/guard time output (bidirectional). a voltage greater than v tst detected at st causes the device to register the detected tone pair and update the output latch. a voltage less than v tst frees the device to accept a new tone pair. the gt output acts to reset the external steering time-constant; its state is a function of est and the voltage on st. 20 24 v dd positive power supply (5v typ.). nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 in+ in- gs vref vss osc1 osc2 nc tone r/w /wr cs vdd st/gt est d3 d2 d1 d0 nc pwdn irq /cp ds/rd rs0 24 pin dip/ssop 27 4 3 2 1 28 26 5 6 7 8 9 10 11 25 24 23 22 21 20 19 17 12 13 14 15 16 18 nc vref vss osc1 osc2 nc nc gs nc in- in+ vdd st/gt est d3 d2 d1 d0 nc pwdn nc tone r/w /wr cs rs0 nc ds/rd irq /cp 28 pin plcc
advance information mt8885 4-53 functional description the mt8885 integrated dtmf transceiver consists of a high performance dtmf receiver with an internal gain setting amplifier and a dtmf generator, which employs a burst counter to synthesize precise tone bursts and pauses. a call progress mode can be selected so that frequencies within the specified passband can be detected. the adaptive micro interface allows microcontrollers, such as the 68hc11, 80c51 and tms370c50, to access the mt8885 internal registers. power down the mt8885 provides enhanced power down functionality to facilitate minimization of supply current consumption. dtmf transmitter and receiver circuit blocks may be independently powered down via register control. when asserted, the rxen control bit powers down all analog and digital circuitry associated solely with the dtmf and call progress receiver. the tout control bit is used to disable the transmitter and put all circuitry associated only with the dtmf transmitter in power down mode. with the tout control bit asserted, the tone output pin is held in a high impedance (floating) state. when both power down control bits are asserted, circuits utilized by both the dtmf transmitter and receiver are also powered down. this includes the crystal oscillators, and the vref generator. in addition, the irq , tone output and data pins are held in a high impedance state. finally, the whole device is put in a power down state when the pwdn pin is asserted. input configuration the input arrangement of the mt8885 provides a differential-input operational amplifier as well as a bias source (v ref ), which is used to bias the inputs at v dd /2. provision is made for connection of a feedback resistor to the op-amp output (gs) for gain adjustment. in a single-ended configuration, the input pins are connected as shown in figure 3. figure 4 shows the necessary connections for a differential input configuration. receiver section separation of the low and high group tones is achieved by applying the dtmf signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies (see table 1). the filters also incorporate notches at 350 hz and 440 hz for exceptional dial tone rejection. each filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting. limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. the outputs of the comparators provide full rail logic swings at the frequencies of the incoming dtmf signals. figure 3 - single-ended input configuration figure 4 - differential input configuration c r in r f in+ in- gs v ref voltage gain (a v ) = r f / r in mt8885 c1 c2 r1 r2 r3 r4 r5 in+ in- gs v ref differential input amplifier c1 = c2 = 10 nf r1 = r4 = r5 = 100 k w r2 = 60k w , r3 = 37.5 k w r3 = (r2r5)/(r2 + r5) voltage gain (a v diff) - r5/r1 input impedance (z in diff) = 2 r1 2 + (1/ w c) 2 mt8885 8,9 17 3,5, 10,11 16, 20, 25 nc no connection. pin description pin # name description 24 28
mt8885 advance information 4-54 0= logic low, 1= logic high table 1. functional encode/decode table following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard dtmf frequencies. a complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. this averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. when the detector recognizes the presence of two valid tones (this is referred to as the signal condition in some industry specifications) the early steering (est) output will go to an active state. any subsequent loss of signal condition will cause est to assume an inactive state. steering circuit before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). this check is performed by an external rc time constant driven by est. a logic high on est causes v c (see figure 5) to rise as the capacitor discharges. provided that the signal condition is maintained (est remains high) for the validation period (t gtp ), v c reaches the threshold f low f high digit d 3 d 2 d 1 d 0 6971209 1 0001 6971336 2 0010 6971477 3 0011 7701209 4 0100 7701336 5 0101 7701477 6 0110 8521209 7 0111 8521336 8 1000 8521477 9 1001 9411336 0 1010 9411209 * 1011 9411477 # 1100 6971633 a 1101 7701633 b 1110 8521633 c 1111 9411633 d 0000 (v tst ) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see table 1) into the receive data register. at this point the gt output is activated and drives v c to v dd . gt continues to drive high as long as est remains high. finally, after a short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has been registered. the status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. if interrupt mode has been selected, the irq /cp pin will pull low when the delayed steering flag is active. the contents of the output latch are updated on an active delayed steering transition. this data is presented to the four bit bidirectional data bus when the receive data register is read. the steering circuit works in reverse to validate the interdigit pause between signals. thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. this facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. figure 5 - basic steering circuit guard time adjustment the simple steering circuit shown in figure 5 is adequate for most applications. component values are chosen according to the following inequalities (see figure 7): t rec 3 t dpmax + t gtpmax - t damin t rec t dpmin + t gtpmin - t damax t id 3 t damax + t gtamax - t dpmin t do t damin + t gtamin - t dpmax the value of t dp is a device parameter (see ac electrical characteristics) and t rec is the minimum v dd v dd st/gt est c1 vc r1 t gta = (r1c1) in (v dd / v tst ) t gtp = (r1c1) in [v dd / (v dd -v tst )] mt8885
advance information mt8885 4-55 signal duration to be recognized by the receiver. a value for c1 of 0.1 f is recommended for most figure 6 - guard time adjustment v dd st/gt est v dd st/gt est c1 r1 r2 c1 r1 r2 t gta = (r1c1) in (v dd /v tst ) t gtp = (r p c1) in [v dd / (v dd -v tst )] r p = (r1r2) / (r1 + r2) t gta = (r p c1) in (v dd /v tst ) t gtp = (r1c1) in [v dd / (v dd -v tst )] r p = (r1r2) / (r1 + r2) a) decreasing tgtp; (tgtp < tgta) b) decreasing tgta; (tgtp > tgta) applications, leaving r1 to be selected by the designer. different steering arrangements may be used to select independent tone present (t gtp ) and tone absent (t gta ) guard times. this may be necessary to meet system specifications which place both accept and reject limits on tone duration and interdigital pause. guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. increasing t rec improves talk-off performance since it reduces the probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. alternatively, a relatively short t rec with a long t do would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. design information for guard time adjustment is shown in figure 6. the receiver timing is shown in figure 7 with a description of the events in figure 9. call progress filter a call progress mode, using the mt8885, can be selected allowing the detection of various tones, which identify the progress of a telephone call on the network. the call progress tone input and dtmf input are common, however, call progress tones can only be detected when cp mode has been selected. figure 7 - receiver timing diagram v in est st/gt rx 0 -rx 3 b3 b2 read status register irq /cp events abcdef t rec t rec t id t do tone #n tone #n + 1 tone #n + 1 t dp t da t gtp t gta t pstrx t pstb3 decoded tone # (n-1) # n # (n + 1) v tst
mt8885 advance information 4-56 figure 9 - description of timing events explanation of events a) tone bursts detected, tone duration invalid, rx data register not updated. b) tone #n detected, tone duration valid, tone decoded and latched in rx data register. c) end of tone #n detected, tone absent duration valid, information in rx data register retained until next valid tone pair. d) tone #n+1 detected, tone duration valid, tone decoded and latched in rx data register. e) acceptable dropout of tone #n+1, tone absent duration invalid, data remains unchanged. f) end of tone #n+1 detected, tone absent duration valid, information in rx data register retained until next valid tone pair. explanation of symbols v in dtmf composite input signal. est early steering output. indicates detection of valid tone frequencies. st/gt steering input/guard time output. drives external rc timing circuit. rx 0 -rx 3 4-bit decoded data in receive data register b3 delayed steering. indicates that valid frequencies have been present/absent for the required guard time thus constituting a valid signal. active low for the duration of a valid dtmf signal. b2 indicates that valid data is in the receive data register. the bit is cleared after the status register is read. irq /cp interrupt is active indicating that new data is in the rx data register. the interrupt is cleared after the status register is read. t rec maximum dtmf signal duration not detected as valid. t rec minimum dtmf signal duration required for valid recognition. t id minimum time between valid sequential dtmf signals. t do maximum allowable dropout during valid dtmf signal. t dp time to detect valid frequencies present. t da time to detect valid frequencies absent. t gtp guard time, tone present. t gta guard time, tone absent. dtmf signals cannot be detected if cp mode has been selected (see table 7). figure 8 indicates the useful detect bandwidth of the call progress filter. frequencies presented to the input, which are within the accept bandwidth limits of the filter, are hard- limited by a high gain comparator with the irq /cp pin serving as the output. the squarewave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. frequencies which are in the reject area will not be detected and consequently the irq /cp pin will remain low. dtmf generator the dtmf transmitter employed in the mt8885 is capable of generating all sixteen standard dtmf tone pairs with low distortion and high accuracy. all frequencies are derived from an external 3.579545 mhz crystal. the sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor d/a converters. the row and column tones are mixed and filtered providing a dtmf signal with low total harmonic distortion and high accuracy. to specify a dtmf signal, data conforming to the encoding format shown in table 1 must be written to the transmit data register. note that this is the same as the receiver output code. the individual tones which are generated (f low and f high ) are referred to as low group and high group tones. as seen from the table, the low group frequencies are 697, 770, 852 and 941 hz. the high group frequencies are 1209, 1336, 1477 and 1633 hz. typically, the high group to low group amplitude ratio (twist) is 2 db to com-pensate for high group attenuation on long loops. figure 8 - call progress response aaaa a aaa a aaa a aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a aaaa a aaa a aaa aaaa aaaa aaaa aaaa aaaa aa a a a a aa level (dbm) frequency (hz) -25 0250500750 = reject = may accept = accept
advance information mt8885 4-57 figure 10 - spectrum plot scaling information 10 db/div start frequency = 0 hz stop frequ ency = 3400 hz marker frequency = 697 hz and 1209 hz the period of each tone consists of 32 equal time segments. the period of a tone is controlled by varying the length of these time segments. during write operations to the transmit data register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmable divider circuitry. this code is used to specify a time segment length, which will ultimately determine the frequency of the tone. when the divider reaches the appropriate count, as determined by the input code, a reset pulse is issued and the counter starts again. the number of time segments is fixed at 32, however, by varying the segment length as described above the frequency can also be varied. the divider output clocks another counter, which addresses the sinewave lookup rom. the lookup table contains codes which are used by the switched capacitor d/a converter to obtain discrete and highly accurate dc voltage levels. two identical circuits are employed to produce row and column tones, which are then mixed using a low noise summing amplifier. the oscillator described needs no start-up time as in other dtmf generators since the crystal oscillator is running continuously thus providing a high degree of tone burst accuracy. a bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 khz. it can be seen from figure 6 that the distortion products are very low in amplitude. burst mode in certain telephony applications it is required that dtmf signals being generated are of a specific duration determined either by the particular application or by any one of the exchange transmitter specifications currently existing. standard dtmf signal timing can be accomplished by making use of the burst mode. the transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. this burst/pause duration is 51 ms1 ms which is a standard interval for autodialer and central office applications. after the burst/pause has been issued, the appropriate bit is set in the status register indicating that the transmitter is ready for more data. the timing described above is available when dtmf mode has been selected. however, when cp mode (call progress mode) is selected, the burst/pause duration is doubled to 102 ms 2 ms. note that when cp mode and burst mode have been selected, dtmf tones may be transmitted only and not received. in applications where a non-standard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and disabling the transmitter. single tone generation a single tone mode is available whereby individual tones from the low group or high group can be generated. this mode can be used for dtmf test equipment applications, acknowledgment tone generation and distortion measurements. refer to control register b description for details.
mt8885 advance information 4-58 table 2. actual frequencies versus standard requirements distortion calculations the mt8885 is capable of producing precise tone bursts with minimal error in frequency (see table 2). the internal summing amplifier is followed by a first- order lowpass switched capacitor filter to minimize harmonic components and intermodulation products. the total harmonic distortion for a single tone can be calculated using equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage. equation 1. thd (%) for a single tone the fourier components of the tone output correspond to v 2f .... v nf as measured on the output waveform. the total harmonic distortion for a dual tone can be calculated using equation 2. v l and v h correspond to the low group amplitude and high group amplitude, respectively and v 2 imd is the sum of all the intermodulation components. the internal switched-capacitor filter following the d/a converter keeps distortion products down to a very low level as shown in figure 10. equation 2. thd (%) for a dual tone active input output frequency (hz) %error specified actual l1 697 699.1 +0.30 l2 770 766.2 -0.49 l3 852 847.4 -0.54 l4 941 948.0 +0.74 h1 1209 1215.9 +0.57 h2 1336 1331.7 -0.32 h3 1477 1471.9 -0.35 h4 1633 1645.0 +0.73 thd (%) = 100 v fundamental v 2 2f + v 2 3f + v 2 4f + .... v 2 nf v 2 l + v 2 h v 2 2l + v 2 3l + .... v 2 nl + v 2 2h + v 2 3h + .. v 2 nh + v 2 imd thd (%) = 100 dtmf clock circuit the internal clock circuit is completed with the addition of a standard television colour burst crystal having a resonant frequency of 3.579545 mhz. a number of mt8885 devices can be connected as shown in figure 11 such that only one crystal is required. alternatively, the osc1 inputs on all devices can be driven from a ttl buffer with the osc2 outputs left unconnected. figure 11 - common crystal connection microprocessor interface the mt8885 design incorporates an adaptive interface, which allows it to be connected to various kinds of microprocessors. key functions of this interface include the following: ? continuous activity on ds/rd is not necessary to update the internal status registers. ? senses whether input timing is that of an intel or motorola controller by monitoring the ds (rd ), r/w (wr ) and cs inputs. ? generates equivalent cs signal for internal operation for all processors. ? differentiates between multiplexed and non- multiplexed microprocessor buses. address and data are latched in accordingly. ? compatible with motorola and intel processors. figure 16 shows the timing diagram for motorola microprocessors with separate address and data buses. members of this microprocessor family include 2 mhz versions of the mc6800, mc6802 and mc6809. for the mc6809, the chip select (cs ) input signal is formed by nanding the (e+q) clocks and address decode output. for the mc6800 and mc6802, cs is formed by nanding vma and address decode output. on the falling edge of cs , the internal logic senses the state of data strobe mt8885 osc1 osc2 mt8885 osc1 osc2 mt8885 osc1 osc2 3.579545 mhz
advance information mt8885 4-59 (ds). when ds is low, motorola processor operation is selected. figure 17 shows the timing diagram for the motorola mc68hc11 (1 mhz) microcontroller. the chip select (cs ) input is formed by nanding address strobe (as ) and address decode output. again, the mt8885 examines the state of ds on the falling edge of cs to determine if the micro has a motorola bus (when ds is low). additionally, the texas instruments tms370cx5x is qualified to have a motorola interface. figure 12(a) summarizes connection of these motorola processors to the mt8885 dtmf transceiver. figures 18 and 19 are the timing diagrams for the intel 8031/8051 (12 mhz) and 8085 (5 mhz) micro- controllers with multiplexed address and data buses. the mt8885 latches in the state of rd on the falling edge of cs . when rd is high, intel processor operation is selected. by nanding the address latch enable (ale) output with the high-byte address (p2) decode output, cs can be generated. figure 12(b) summarizes the connection of these intel processors to the mt8885 transceiver. note: the adaptive micro interface relies on high- to-low transition on cs to recognize the microcontroller interface and this pin must not be tied permanently low. the adaptive micro interface provides access to five internal registers. the read-only receive data register contains the decoded output of the last valid dtmf digit received. data entered into the write-only transmit data register will determine which tone pair is to be generated (see table 1 for coding details). transceiver control is accomplished with two control registers (see tables 6 and 7), cra and crb, which have the same address. a write operation to crb is executed by first setting the most significant bit (b3) in cra. the following write operation to the same address will then be directed to crb, and subsequent write cycles will be directed back to cra. the read-only status register indicates the current transceiver state (see table 8). a software reset must be included at the beginning of all programs to initialize the control registers upon power-up or power reset (see figure 14). refer to tables 4-7 for bit descriptions of the two control registers. the multiplexed irq /cp pin can be programmed to generate an interrupt upon validation of dtmf signals or when the transmitter is ready for more data (burst mode only). alternatively, this pin can be configured to provide a square-wave output of the call progress signal. the irq /cp pin is an open drain output and requires an external pull-up resistor (see figure 13). figure 12 a) & b) - mt8885 interface connections for various intel and motorola micros mc6800/6802 mt8885 mt8885 a0-a15 vma d0-d3 rw mc68hc11 mc6809 mt8885 mt8885 8031/8051 8080/8085 f 2 cs rs0 d0-d3 r/w /wr ds/rd a8-a15 as ad0-ad3 rw cs rs0 d0-d3 r/w /wr ds/rd ds a0-a15 q e d0-d3 r/w cs rs0 d0-d3 r/w /wr ds/rd a8-a15 ale p0 rd wr cs d0-d3 rs0 ds/rd r/w /wr (a) (b)
mt8885 advance information 4-60 table 3. internal register functions table 4. cra bit positions table 5. crb bit positions motorola intel rs0 r/w wr rd function 0001 write to transmit data register 0110 read from receive data register 1001 write to control register 1110 read from status register b3 b2 b1 b0 rsel irq cp/dtmf tout b3 b2 b1 b0 c/r s/d test burst enable table 6. control register a description bit name description b0 tout tone output control. a logic high enables the tone output; a logic low turns the tone output off and places the complete dtmf transmitter circuit in power down mode. this bit controls all transmit tone functions. b1 cp/dtmf call progress or dtmf mode select. a logic high enables the receive call progress mode; a logic low enables dtmf mode. in dtmf mode the device is capable of receiving and transmitting dtmf signals. in cp mode a retangular wave representation of the received tone signal will be present on the irq /cp output pin if irq has been enabled (control register a, b2=1). in order to be detected, cp signals must be within the bandwidth specified in the ac electrical characteristics for call progress. note: dtmf signals cannot be detected when cp mode is selected. b2 irq interrupt enable. a logic high enables the interrupt function; a logic low de-activates the interrupt function. when irq is enabled and dtmf mode is selected (control register a, b1=0), the irq /cp output pin will go low when either 1) a valid dtmf signal has been received for a valid guard time duration, or 2) the transmitter is ready for more data (burst mode only). b3 rsel register select. a logic high selects control register b for the next write cycle to the control register address. after writing to control register b, the following control register write cycle will be directed to control register a.
advance information mt8885 4-61 ta ble 7 . control register b description ta ble 8 . status register description bit name description b0 burst burst mode select. a logic high de-activates burst mode; a logic low enables burst mode. when activated, the digital code representing a dtmf signal (see table 1) can be written to the transmit register, which will result in a transmit dtmf tone burst and pause of equal durations (typically 51 msec). following the pause, the status register will be updated (b1 - transmit data register empty), and an interrupt will occur if the interrupt mode has been enabled. when cp mode (control register a, b1) is enabled the normal tone burst and pause durations are extended from a typical duration of 51 msec to 102 msec. when burst is high (de-activated) the transmit tone burst duration is determined by the tout bit (control register a, b0). b1 rxen this bit enables the dtmf and call progress tone receivers. a logic low enables both circuits. a logic high deactivates and puts both receiver circuits into power down mode. b2 s/d single or dual tone generation. a logic high selects the single tone output; a logic low selects the dual tone (dtmf) output. the single tone generation function requires further selection of either the row or column tones (low or high group) through the c/r bit (control register b, b3). b3 c/r column or row tone select. a logic high selects a column tone output; a logic low selects a row tone output. this function is used in conjunction with the s/d bit (control register b, b2). bit name status flag set status flag cleared b0 irq interrupt has occurred. bit one (b1) or bit two (b2) is set. interrupt is inactive. cleared after status register is read. b1 transmit data register empty (burst mode only) pause duration has terminated and transmitter is ready for new data. cleared after status register is read or when in non-burst mode. b2 receive data register full valid data is in the receive data register. cleared after status register is read. b3 delayed steering set upon the valid detection of the absence of a dtmf signal. cleared upon the detection of a valid dtmf signal.
mt8885 advance information 4-62 figure 13 - application circuit (single-ended input) in+ in- gs vref vss osc1 osc2 tone r/w /wr cs vdd st/gt est d3 d2 d1 d0 irq /cp ds/rd rs0 dtmf/cp input dtmf output c1 r1 r2 x-tal r l v dd c3 c2 r4 r3 to m p or m c notes: r1, r2 = 100 k w 1% r3 = 374 w 1% r4 = 3.3 k w 10% r l = 10 k w (min.) c1 = 100 nf 5% c2 = 100 nf 5% c3 = 100 nf 10%* x-tal = 3.579545 mhz * microprocessor based systems can inject undesirable noise into the supply rails. the performance of the mt8885 can be optimized by keeping noise on the supply rails to a minimum. the decoupling capacitor (c3) should be connected close to the device and ground loops should be avoided. mt8885 pwdn nc nc nc
advance information mt8885 4-63 figure 14 - application notes initialization procedure a software reset must be included at the beginning of all programs to initialize the control registers after power up. description: motorola intel data rs0 r/w wr rd b3 b2 b1 b0 1) read status register 1 1 1 0 x x x x 2) write to control register 1 0 0 1 0 0 0 0 3) write to control register 1 0 0 1 0 0 0 0 4) write to control register 1 0 0 1 1 0 0 0 5) write to control register 1 0 0 1 0 0 0 0 6) read status register 1 1 1 0 x x x x typical control sequence for burst mode applications transmit dtmf tones of 50 ms burst/50 ms pause and receive dtmf tones. sequence: rs0 r/w wr rd b3 b2 b1 b0 1) write to control register a 1 0 0 1 1 1 0 1 (tone out, dtmf, irq , select control register b) 2) write to control register b 1 0 0 1 0 0 0 0 (burst mode) 3) write to transmit data register 0 0 0 1 0 1 1 1 (send a digit 7) 4) wait for an interrupt or poll status register 5) read the status register 1 1 1 0 x x x x -if bit 1 is set, the tx is ready for the next tone, in which case ... write to transmit register 0 0 0 1 0 1 0 1 (send a digit 5) -if bit 2 is set, a dtmf tone has been received, in which case .... read the receive data register 0 1 1 0 x x x x -if both bits are set ... read the receive data register 0 1 1 0 x x x x write to transmit data register 0 0 0 1 0 1 0 1 note: in the tx burst mode, status register bit 1 will not be set until 100 ms ( 2 ms) after the data is written to the tx data register. in extended burst mode this time will be doubled to 200 ms ( 4 ms)
mt8885 advance information 4-64 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c and for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless oth erwise stated. ? typical figures are at 25 c, v dd =5v and for design aid only: not guaranteed and not subject to production testing. * see notes following ac electrical characteristics tables. absolute maximum ratings * parameter symbol min max units 1 power supply voltage v dd -v ss v dd 6v 2 voltage on any pin v i v ss -0.3 v dd +0.3 v 3 current at any pin (except v dd and v ss )10ma 4 storage temperature t st -65 +150 c 5 package power dissipation p d 1000 mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. parameter sym min typ ? max units test conditions 1 positive power supply v dd 4.75 5.00 5.25 v 2 operating temperature t o -40 +85 c 3 crystal clock frequency f clk 3.575965 3.579545 3.583124 mhz dc electrical characteristics ? - v ss =0 v. characteristics sym min typ ? max units test conditions 1 s u p operating supply voltage v dd 4.75 5.0 5.25 v 2 operating supply current i dd 7.0 11 ma 3 standby supply current 25 a pwdn= v dd 4 i n p u t s high level input voltage (osc1) v iho 3.5 v note 9* 5 low level input voltage (osc1) v ilo 1.5 v note 9* 6 steering threshold voltage v tst 2.2 2.3 2.5 v v dd =5v 7 o u t p u t s low level output voltage (osc2) v olo 0.1 v no load note 9* 8 high level output voltage (osc2) v oho 4.9 v no load note 9* 9 output leakage current (irq) i oz 110 av oh =2.4 v 10 v ref output voltage v ref 2.4 2.5 2.6 v no load, v dd =5v 11 v ref output resistance r or 1.3 k w 12 d i g i t a l low level input voltage v il 0.8 v 13 high level input voltage v ih 2.0 v 14 input leakage current i iz 10 av in =v ss to v dd 15 data bus source current i oh -1.4 -6.6 ma v oh =2.4v 16 sink current i ol 2.0 4.0 ma v ol =0.4v 17 est and st/gt source current i oh -0.5 -3.0 ma v oh =4.6v 18 sink current i ol 24 mav ol =0.4v 19 irq / cp sink current i ol 416 mav ol =0.4v
advance information mt8885 4-65 ? typical figures are at 25c and for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions (unless oth erwise stated) using the test circuit shown in figure 13. ? characteristics are over recommended operating conditions unless oth erwise stated. ? typical figures are at 25c, v dd = 5v, and for design aid only: not guaranteed and not subject to production testing. * *see notes following ac electrical characteristics tables. electrical characteristics gain setting amplifier - voltages are with respect to ground (v ss ) unless otherwise stated, v ss = 0v, v dd =5v, t o =25c. characteristics sym min typ ? max units test conditions 1 input leakage current i in 100 na v ss v in v dd 2 input resistance r in 10 m w 3 input offset voltage v os 25 mv 4 power supply rejection psrr 60 db 1 khz 5 common mode rejection cmrr 60 db 0.75 v in 4.25v 6 dc open loop voltage gain a vol 65 db 7 unity gain bandwidth bw 1.5 mhz 8 output voltage swing v o 4.5 v pp r l 3 100 k w to v ss 9 allowable capacitive load (gs) c l 100 pf 10 allowable resistive load (gs) r l 50 k w 11 common mode range v cm 3.0 v pp no load mt8885 ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units notes* 1 r x valid input signal levels (each tone of composite signal) -29 +1 dbm 1,2,3,5,6 27.5 869 mv rms 1,2,3,5,6 ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. f c =3.579545 mhz characteristics sym min typ ? max units notes* 1 r x positive twist accept 8 db 2,3,6,9 2 negative twist accept 8 db 2,3,6,9 3 freq. deviation accept 1.5% 2hz 2,3,5 4 freq. deviation reject 3.5% 2,3,5 5 third tone tolerance -16 db 2,3,4,5,9,10 6 noise tolerance -12 db 2,3,4,5,7,9,10 7 dial tone tolerance 22 db 2,3,4,5,8,9
mt8885 advance information 4-66 ? characteristics are over recommended operating conditions unless oth erwise stated ? typical figures are at 25c, v dd =5v, and for design aid only: not guaranteed and not subject to production testing ? characteristics are over recommended operating conditions unless oth erwise stated ? typical figures are at 25c, v dd =5v, and for design aid only: not guaranteed and not subject to production testing ? timing is over recommended temperature & power supply voltages. ? typical figures are at 25c and for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - call progress - voltages are with respect to ground (v ss ), unless otherwise stated. characteristics sym min typ ? max units conditions 1 accept bandwidth f a 310 500 hz @ -25 dbm, note 9 2 lower freq. (reject) f lr 290 hz @ -25 dbm 3 upper freq. (reject) f hr 540 hz @ -25 dbm 4 call progress tone detect level (total power) -30 dbm ac electrical characteristics ? - dtmf reception - typical dtmf tone accept and reject requirements. actual values are user selectable as per figures 5, 6 and 7. characteristics sym min typ ? max units conditions 1 minimum tone accept duration t rec 40 ms 2 maximum tone reject duration t rec 20 ms 3 minimum interdigit pause duration t id 40 ms 4 maximum tone drop-out duration t od 20 ms ac electrical characteristics ? - voltages are with respect to ground (v ss ), unless otherwise stated. characteristics sym min typ ? max units conditions 1 t o n e i n tone present detect time t dp 3 11 14 ms note 11 2 tone absent detect time t da 0.5 4 8.5 ms note 11 3 delay st to b3 t pstb3 13 s see figure 7 4 delay st to rx 0 -rx 3 t pstrx 8 s see figure 7 5 t o n e o u t tone burst duration t bst 50 52 ms dtmf mode 6 tone pause duration t ps 50 52 ms dtmf mode 7 tone burst duration (extended) t bste 100 104 ms call progress mode 8 tone pause duration (extended) t pse 100 104 ms call progress mode 9 high group output level v hout -6.1 -2.1 dbm r l =10k w 10 low group output level v lout -8.1 -4.1 dbm r l =10k w 11 pre-emphasis dbp 0 2 3 db r l =10k w 12 output distortion (single tone) thd -35 db 25 khz bandwidth 13 r l =10k w 14 frequency deviation f d 0.7 1.5 % f c =3.579545 mhz 15 output load resistance r lt 10 50 k w 16 x t a l crystal/clock frequency f c 3.5759 3.5795 3.5831 mhz 17 clock input rise and fall time t clrf 110 ns ext. clock 18 clock input duty cycle dc cl 40 50 60 % ext. clock 19 capacitive load (osc2) c lo 30 pf
advance information mt8885 4-67 ? characteristics are over recommended operating conditions unless oth erwise stated ? typical figures are at 25c, v dd =5v, and for design aid only: not guaranteed and not subject to production testing notes: 1) dbm=decibels above or below a reference power of 1 mw into a 600 ohm load. 2) digit sequence consists of all 16 dtmf tones. 3) tone duration=40 ms. tone pause=40 ms. 4) nominal dtmf frequencies are used. 5) both tones in the composite signal have an equal amplitude. 6) the tone pair is deviated by 1.5 %2 hz. 7) bandwidth limited (3 khz) gaussian noise. 8) the precise dial tone frequencies are 350 and 440 hz (2 %). 9) guaranteed by design and characterization. not subject to production testing. 10) referenced to the lowest amplitude tone in the dtmf signal. 11) for guard time calculation purposes. figure 15 - ds/rd /wr clock pulse ac electrical characteristics ? - mpu interface - voltages are with respect to ground (v ss ), unless otherwise stated. characteristics sym min typ ? max units conditions 1ds/rd /wr clock frequency f cyc 4.0 mhz figure 15 2ds/rd /wr cycle period t cyc 250 ns figure 15 3ds/rd /wr low pulse width t cl 150 ns figure 15 4ds/rd /wr high pulse width t ch 100 ns figure 15 5ds/rd /wr rise and fall time t r, t f 20 ns figure 15 6r/w setup time t rws 23 ns figures 16 & 17 7r/w hold time t rwh 20 ns figures 16 & 17 8 address setup time (rs0) t as 0 ns figures 16 - 19 9 address hold time (rs0) t ah 40 20 ns figures 16 - 19 10 data hold time (read) t dhr 22 ns figures 16 - 19 11 ds/rd to valid data delay (read) t ddr 100 ns figures 16 - 19 12 data setup time (write) t dsw 45 ns figures 16 - 19 13 data hold time (write) t dhw 10 ns figures 16 - 19 14 chip select setup time t css 45 35 ns figures 16 - 19 15 chip select hold time t csh 40 ns figures 16 - 19 16 input capacitance (data bus) c in 5pf 17 output capacitance (irq /cp) c out 5pf t cyc t r t ch t cl ds/rd /wr t f
mt8885 advance information 4-68 figure 16 - mc6800/mc6802/mc6809 timing diagram t dsw is from data to ds falling edge; t csh is from ds rising edge to cs rising edge. figure 17 - mc68hc11 bus timing (with multiplexed address and data buses) ds q clk* a0-a15 (rs0) r/w (read) read data (d3-d0) r/w (write) write data (d3-d0) cs = (e + q).addr [mc6809] cs = vma.addr [mc6800, mc6802] *microprocessor pin t rws t rwh 16 bytes of addr t ddr t dsw t dhw t csh t css t as t ah t as t css t csh t ah t dhr ds r/w read ad3-ad0 (rs0, d0-d3) write ad3-ad0 (rs0-d0-d3) addr * non-mux as * cs = as.addr * microprocessor pins t rws t rwh t as t ddr t dhr data data t ah t dsw t dhw t csh t css high byte of addr addr addr
advance information mt8885 4-69 figure 18 - 8031/8051/8085 read timing diagram figure 19 - 8031/8051/8085 write timing diagram ale* rd p0* (rs0, d0-d3) p2 * (addr) cs = ale.addr * microprocessor pins t css t as t ah t ddr t dhr data a8-a15 add ress t csh a0-a7 ale* wr p0* (rs0, d0-d3) p2 * (addr) cs = ale.addr * microprocessor pins t css t as t ah t dsw t dhw data a8-a15 address t csh a0-a7
mt8885 advance information 4-70 notes:

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